Compositions and methods for chemical-mechanical polishing (CMP) of the surface of a substrate are well known in the art. Polishing compositions (also known as polishing slurries, CMP slurries, and CMP compositions) for CMP of surfaces of semiconductor substrates (e.g., integrated circuits) typically contain an abrasive, various additive compounds, and the like.
In general, CMP involves the concurrent chemical and mechanical abrasion of surface, e.g., abrasion of an overlying first layer to expose the surface of a non-planar second layer on which the first layer is formed. One such process is described in U.S. Pat. No. 4,789,648 to Beyer et al. Briefly, Beyer et al., discloses a CMP process using a polishing pad and a slurry to remove a first layer at a faster rate than a second layer until the surface of the overlying first layer of material becomes coplanar with the upper surface of the covered second layer. More detailed explanations of chemical mechanical polishing are found in U.S. Pat. No. 4,671,851, U.S. Pat. No. 4,910,155 and U.S. Pat. No. 4,944,836.
In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, urging the substrate against the polishing pad. The pad and carrier, with its attached substrate, are moved relative to one another. The relative movement of the pad and substrate serves to abrade the surface of the substrate to remove a portion of the material from the substrate surface, thereby polishing the substrate. The polishing of the substrate surface typically is further aided by the chemical activity of the polishing composition (e.g., by oxidizing agents, acids, bases, or other additives present in the CMP composition) and/or the mechanical activity of an abrasive suspended in the polishing composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide.
U.S. Pat. No. 5,527,423 to Neville, et al., for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface of the metal layer with a polishing slurry comprising high purity fine metal oxide particles suspended in an aqueous medium. Alternatively, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,489,233 to Cook et al. discloses the use of polishing pads having a surface texture or pattern, and U.S. Pat. No. 5,958,794 to Bruxvoort et al. discloses a fixed abrasive polishing pad.
A semiconductor wafer typically includes a substrate, such as silicon or gallium arsenide, on which a plurality of transistors have been formed. Transistors are chemically and physically connected to the substrate by patterning regions in the substrate and layers on the substrate. The transistors and layers are separated by interlevel dielectrics (ILDs), comprised primarily of some form of silicon oxide (SiO2). The transistors are interconnected through the use of well-known multilevel interconnects. Typical multilevel interconnects are comprised of stacked thin-films consisting of one or more of the following materials: titanium (Ti), titanium nitride (TiN), tantalum (Ta), aluminum-copper (Al—Cu), aluminum-silicon (Al—Si), copper (Cu), tungsten (W), doped polysilicon (poly-Si), and various combinations thereof. In addition, transistors or groups of transistors are isolated from one another, often through the use of trenches filled with an insulating material such as silicon dioxide, silicon nitride, and/or polysilicon.
The traditional technique for forming interconnects has been improved by the method disclosed in U.S. Pat. No. 4,789,648 to Chow et al., which relates to a method for producing coplanar multilevel metal/insulator films on a substrate. This technique, which has gained wide interest and produces multilevel interconnects, uses chemical mechanical polishing to planarize the surface of the metal layers or thin-films during the various stages of device fabrication.
Although many of the known CMP slurry compositions are suitable for limited purposes, the conventional tend to exhibit unacceptable polishing rates and corresponding selectivity levels to insulator materials used in wafer manufacture. In addition, known polishing slurries tend to produce poor film removal traits for the underlying films or produce deleterious film-corrosion, which leads to poor manufacturing yields.
As the technology for integrated circuit devices advances, traditional materials are being used in new and different ways to achieve the level of performance needed for advanced integrated circuits. In particular, silicon nitride, silicon oxide, and polysilicon are being used in various combinations to achieved new and ever more complex device configurations. In general, the structural complexity and performance characteristics vary across different applications. There is an ongoing need for methods and compositions that allow for the removal rates of silicon nitride, silicon oxide and polysilicon materials to be adjusted or tuned during CMP to meet the polishing requirements for particular IC devices.
For example, there is a continuing need to achieve rapid silicon nitride removal rates for many IC device applications. Traditional polishing slurries have been designed for “stop on silicon nitride” applications, such as in shallow trench isolation (STI). Typical STI slurries utilize silica abrasives at high pH and high abrasive concentrations to achieve reasonable silicon nitride removal rates. The use of high abrasive particle concentrations has been associated with a high level of scratch defects in the polished devices.
Co-owned, co-pending U.S. patent application Ser. No. 11/374,238 to Chen et al. describes novel polishing compositions having a pH of about 1 to about 6 including an abrasive in combination with certain acidic components (e.g., combinations of malonic acid and an aminocarboxylic acid; stannate salts; uric acid; phenylacetic acid; or combinations of malonic acid, an aminocarboxylic acid, and sulfate) to polish silicon nitride substrates.
There is an ongoing need to develop new polishing methods and compositions that provide relatively high rates of removal of silicon nitride. The present invention provides such improved polishing methods and compositions. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.